// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  snps_phy_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:15 Create file
// ******************************************************************************

#ifndef __SNPS_PHY_REG_REG_OFFSET_H__
#define __SNPS_PHY_REG_REG_OFFSET_H__

/* SNPS_PHY_REG Base address of Module's Register */
#define HiPCIECTRL40V200_SNPS_PHY_REG_BASE                       (0x80000)

/******************************************************************************/
/*                      HiPCIECTRL40V200 SNPS_PHY_REG Registers' Definitions                            */
/******************************************************************************/

#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RESET_REG                          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x800) /* phy_reset */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PCS_LANE_RESET_REG                     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x804) /* pcs_lane_reset */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PIPE_LANE_PROTOCOL_CTRL_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x808) /* pipe_lane_protocol_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_CR_PARA_SEL_REG                        (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x80C) /* cr_para_sel */
#define HiPCIECTRL40V200_SNPS_PHY_REG_UPCS_PIPE_CFG_REG                      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x810) /* upcs_pipe_cfg */
#define HiPCIECTRL40V200_SNPS_PHY_REG_EXT_PCLK_REQ_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x814) /* ext_pclk_req */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PCS_LNAEX_CLKREQ_N_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x818) /* pcs_lanex_clkreq_n */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PCS_LNNEX_LINK_NUM_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x81C) /* pcs_lanex_link_num */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PCS_LNNEX_PHY_SCR_SEL_REG              (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x820) /* pcs_lanex_phy_scr_sel */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PG_MODE_EN_REG                     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x824) /* phy_pg_mode_en */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_LANEX_TX2RX_SER_LB_EN_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x828) /* phy_lanex_tx2rx_ser_lb_en */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_LANEX_RX2TX_PAR_LB_EN_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x82C) /* phy_lanex_rx2tx_par_lb_en */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PCS_RX_DISABLE_REG                     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x830) /* pcs_rx_disable */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PCS_TX_DISABLE_REG                     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x834) /* pcs_tx_disable */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_TERMINATION_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x838) /* phy_rx_termination */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PIPE_LNAEX_POWER_PRESENT_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x83C) /* pipe_lanex_power_present */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PCS_PWR_CTRL_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x840) /* pcs_pwr_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PMA_PWR_CTRL_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x844) /* pma_pwr_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_UPCS_PWR_CTRL_REG                      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x848) /* upcs_pwr_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_LNAEX_POWER_PRESENT_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x84C) /* phy_lanex_power_present */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ANA_PWR_CTRL_REG                   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x850) /* phy_ana_pwr_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_BYPASS_REG                    (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x854) /* phy_sram_bypasst */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_INIT_STATUS_REG               (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x858) /* phy_sram_init_status */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_REF_CLK_CTRL_REG                   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x85C) /* phy_ref_clk_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RTUNE_CTRL_REG                     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x860) /* phy_retume_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TEST_CTRL_REG                      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x864) /* phy_test_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLA_CTRL_REG                     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x868) /* phy_mplla_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLB_CTRL_REG                     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x86C) /* phy_mpllb_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_ALIGN_DETECT_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x870) /* phy_rx_align_detect */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_STAND_BY_REG                    (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x874) /* phy_rx_stand_by */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_ECC_CTRL_REG                  (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x878) /* phy_sram_ecc_insert */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_ECC_ERR_LOG_REG               (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x87C) /* phy_sram_ecc_error_log */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_ECC_ERR_INT_STATUS_REG        (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x880) /* phy_sram_ecc_error_int */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_ECC_ERR_INT_RO_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x884) /* phy_sram_ecc_error_int_ro */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_ECC_ERR_INT_MASK_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x888) /* phy_sram_ecc_error_int_mask */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_SRAM_ECC_ERR_SET_REG               (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x88C) /* phy_sram_ecc_error_int_set */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV0_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x890) /* phy_eco_rsv0 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV1_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x894) /* phy_eco_rsv1 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV2_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x898) /* phy_eco_rsv2 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV3_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x89C) /* phy_eco_rsv3 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV4_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8A0) /* phy_eco_rsv4 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV5_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8A4) /* phy_eco_rsv5 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV6_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8A8) /* phy_eco_rsv6 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_ECO_RSV7_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8AC) /* phy_eco_rsv7 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_EXT_CTRL_SEL_REG                   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8B0) /* phy_ext_ctrl_sel */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_BS_OVERRIDE_CTRL_REG               (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8B4) /* phy_bs_override_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLA_BANDWIDTH_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8B8) /* phy_mplla_bandwidth */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLA_CLK_CTRL_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8BC) /* phy_mplla_clk_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLA_DIV_CTRL_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8C0) /* phy_mplla_clk_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLA_SSC_CTRL_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8C4) /* phy_mplla_ssc_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLB_BANDWIDTH_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8C8) /* phy_mpllb_bandwidth */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLB_CLK_CTRL_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8CC) /* phy_mpllb_clk_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLB_DIV_CTRL_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8D0) /* phy_mpllb_clk_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_MPLLB_SSC_CTRL_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8D4) /* phy_mpllb_ssc_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_EXT_REF_DIV2_EN_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8D8) /* phy_ext_ref_div2_en */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_EXT_REF_RANGE_REG                  (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8DC) /* phy_ext_ref_range */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_AFE_CTRL_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8E0) /* phy_afe_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_DFE_CTRL_REG                       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8E4) /* phy_dfe_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_AFE_GAIN_CTRL_GEN12_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8E8) /* phy_afe_gain_ctrl_gen12 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_AFE_GAIN_CTRL_GEN34_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8EC) /* phy_afe_gain_ctrl_g34 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_ATT_LVL_GEN12_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8F0) /* phy_rx_eq_att_lvl_gen12 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_ATT_LVL_GEN34_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8F4) /* phy_rx_eq_att_lvl_gen34 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_CTLE_BOOST_GEN1_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8F8) /* phy_rx_eq_ctle_boost_gen1 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_CTLE_BOOST_GEN2_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x8FC) /* phy_rx_eq_ctle_boost_gen2 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_CTLE_BOOST_GEN3_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x900) /* phy_rx_eq_ctle_boost_gen3 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_CTLE_BOOST_GEN4_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x904) /* phy_rx_eq_ctle_boost_gen4 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_DELTA_IQ_GEN12_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x908) /* phy_rx_eq_delta_iq_gen12 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_DELTA_IQ_GEN34_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x90C) /* phy_rx_eq_delta_iq_gen34 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_DFE_TAP1_GEN1_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x910) /* phy_rx_eq_dft_tap1_gen1 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_DFE_TAP1_GEN2_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x914) /* phy_rx_eq_dft_tap1_gen2 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_DFE_TAP1_GEN3_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x918) /* phy_rx_eq_dft_tap1_gen3 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_DFE_TAP1_GEN4_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x91C) /* phy_rx_eq_dft_tap1_gen4 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_LOS_CTRL_REG                    (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x920) /* phy_rx_los_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_REF_LD_VAL_CTRL_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x924) /* phy_ref_ld_val_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_TERM_CTRL_REG                   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x928) /* phy_rx_term_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_VCO_LD_VAL_CTRL_GEN12_REG       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x92C) /* phy_rx_vco_ld_val_ctrl_gen34 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_VCO_LD_VAL_CTRL_GEN34_REG       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x930) /* phy_rx_vco_ld_val_ctrl_gen34 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_VFRE_CTRL_REG                   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x934) /* phy_rx_vref_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_PRE_GEN1_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x938) /* phy_tx_eq_pre_gen1 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_PRE_GEN2_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x93C) /* phy_tx_eq_pre_gen2 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_PRE_GEN3_REG                 (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x940) /* phy_tx_eq_pre_gen3 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_MAIN_GEN1_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x944) /* phy_tx_eq_main_gen1 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_MAIN_GEN2_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x948) /* phy_tx_eq_main_gen2 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_MAIN_GEN3_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x94C) /* phy_tx_eq_main_gen3 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_POST_GEN1_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x950) /* phy_tx_eq_post_gen1 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_POST_GEN2_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x954) /* phy_tx_eq_post_gen2 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_POST_GEN3_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x958) /* phy_tx_eq_post_gen3 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_OVRD_CTRL_GEN12_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x95C) /* phy_tx_eq_ovrd_ctrl_gen12 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_EQ_OVRD_CTRL_GEN3_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x960) /* phy_tx_eq_ovrd_ctrl_gen3 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_IBOOST_LVL_CTRL_REG             (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x964) /* phy_tx_iboost_lvl_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_VBOOST_LVL_CTRL_REG             (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x968) /* phy_tx_vboost_lvl_ctrl */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_TERM_CTRL_REG                   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x96C) /* phy_tx_eq_ovrd_ctrl_gen12 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_VALID_OVERRIDE_REG              (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x970) /* phy_rx_valid_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_VALID_OVERRIDE_VALUE_REG        (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x974) /* phy_rx_valid_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_ELECIDLE_OVERRIDE_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x978) /* phy_rx_elecidle_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_ELEIDLE_OVERRIDE_VALUE_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x97C) /* phy_rx_elecidle_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_ELEIDLE_MODE_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x980) /* phy_rx_elecidle_mode */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX0_ELEIDLE_DELAY_TIME_REG         (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x984) /* phy_rx0_elecidle_delay_time */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX1_ELEIDLE_DELAY_TIME_REG         (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x988) /* phy_rx1_ecidle_delay_time */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX2_ELEIDLE_DELAY_TIME_REG         (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x98C) /* phy_rx2_elecidle_delay_time */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX3_ELEIDLE_DELAY_TIME_REG         (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x990) /* phy_rx3_elecidle_delay_time */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_FIG_MERIT_OVERRIDE_REG       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x994) /* pipe_rx0_eq_fig_merit_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_EQ_FIG_MERIT_OVERRIDE_VALUE_REG (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x998) /* pipe_rx0_eq_fig_merit_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_STATUS_OVERRIDE_REG             (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x99C) /* pipe_rx_status_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_STATUS_OVERRIDE_VALUE_REG       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9A0) /* pipe_rx_status_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_STATUS_OVERRIDE_REG                (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9A4) /* pipe_phystatus_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_STATUS_OVERRIDE_VALUE_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9A8) /* pipe_phystatus_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_POWERDOWN_OVERRIDE_REG             (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9AC) /* pipe_poweerdown_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_POWERDOWN_OVERRIDE_VALUE_REG       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9B0) /* pipe_poweerdown_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RATE_OVERRIDE_REG                  (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9B4) /* pipe_rate_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RATE_OVERRIDE_VALUE_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9B8) /* pipe_rate_verride_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_POLARITY_OVERRIDE_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9BC) /* pipe_rx_polarity_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RX_POLARITY_OVERRIDE_VALUE_REG     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9C0) /* pipe_rx_polarity_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_COMPLIANCE_OVERRIDE_REG         (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9C4) /* pipe_tx_compliance_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_COMPLIANCE_OVERRIDE_VALUE_REG   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9C8) /* pipe_tx_compliance_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_ELECIDLE_OVERRIDE_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9CC) /* pipe_tx_elecidle_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_ELECIDLE_OVERRIDE_VALUE_REG     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9D0) /* pipe_tx_elecidle_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_MARGIN_OVERRIDE_REG             (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9D4) /* pipe_tx_margin_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_MARGIN_OVERRIDE_VALUE_REG       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9D8) /* pipe_tx_margin_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_DEEMPH_OVERRIDE_REG             (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9DC) /* pipe_tx_deemph_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX0_DEEMPH_OVERRIDE_VALUE_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9E0) /* pipe_tx0_deemph_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX1_DEEMPH_OVERRIDE_VALUE_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9E4) /* pipe_tx1_deemph_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX2_DEEMPH_OVERRIDE_VALUE_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9E8) /* pipe_tx2_deemph_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX3_DEEMPH_OVERRIDE_VALUE_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9EC) /* pipe_tx3_deemph_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_DETECTRX_OVERRIDE_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9F0) /* pipe_tx_detectrx_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_TX_DETECTRX_OVERRIDE_VALUE_REG     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9F4) /* pipe_tx_detectrx_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_FORCE_RXDETECT_RESULT_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9F8) /* phy_force_rxdetect_result */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_FORCE_RXDETECT_RESULT_VALUE_REG    (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0x9FC) /* phy_force_rxdetect_result_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_SRIS_MODE_EN_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA00) /* pipe_rx_sris_mode_en */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_STATUS_DEBUG_EN_REG        (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA04) /* pipe_rx_status_debug_en */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_STATUS_DEBUG_MODE_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA08) /* pipe_rx_status_debug_mode */
#define HiPCIECTRL40V200_SNPS_PHY_REG_RESVERED_REG                           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA0C) /* reserved */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RXSTATUS_ERR_INT_STATUS_REG        (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA10) /* pipe_rx_status_err_int_status */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RXSTATUS_ERR_INT_RO_REG            (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA14) /* pipe_rx_status_error_int_ro */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RXSTATUS_ERR_INT_MASK_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA18) /* pipe_rx_status_error_int_mask */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_RXSTATUS_ERR_SET_REG               (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA1C) /* pipe_rx_status_error_int_set */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX0_STATUS_ERR_COUNT_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA20) /* pipe_rx_status_err_count */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX1_STATUS_ERR_COUNT_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA24) /* pipe_rx_status_err_count */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX2_STATUS_ERR_COUNT_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA28) /* pipe_rx_status_err_count */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX3_STATUS_ERR_COUNT_REG      (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA2C) /* pipe_rx_status_err_count */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_EYE_EVAL_REQ_REG           (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA30) /* pipe_rx_eye_eval_req */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_EYE_EVAL_DONE_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA34) /* pipe_rx_eye_eval_done */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_EQ_FIG_MERIT_VALUE_REG     (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA38) /* pipe_rx_eq_fig_merit_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_EQ_EVAL_VALUE_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA3C) /* pipe_rx_eq_eval_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_EQ_EVAL_OVERRIDE_REG       (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA40) /* pipe_rx_eq_eval_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_RX_EQ_EVAL_OVERRIDE_VALUE_REG (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA44) /* pipe_rx_eq_eval_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX_EQ_FS_OVERRIDE_REG         (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA48) /* pipe_tx_fs_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX_EQ_FS_OVERRIDE_VALUE_REG   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA4C) /* pipe_tx_fs_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX_EQ_LF_OVERRIDE_REG         (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA50) /* pipe_tx_lf_override */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX_EQ_LF_OVERRIDE_VALUE_REG   (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA54) /* pipe_tx_lf_override_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX0_DEEMPH_VALUE_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA58) /* pipe_tx0_deemph_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX1_DEEMPH_VALUE_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA5C) /* pipe_tx1_deemph_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX2_DEEMPH_VALUE_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA60) /* pipe_tx2_deemph_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_TX3_DEEMPH_VALUE_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA64) /* pipe_tx3_deemph_value */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_EBUFER_LOCATION0_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA68) /* pipe_rx_ebuff_location0 */
#define HiPCIECTRL40V200_SNPS_PHY_REG_PHY_PIPE_EBUFER_LOCATION1_REG          (HiPCIECTRL40V200_SNPS_PHY_REG_BASE + 0xA6C) /* pipe_rx_ebuff_location1 */

#endif // __SNPS_PHY_REG_REG_OFFSET_H__
